PIC16C711-04/P【PDF 127/177 页】IC MCU OTP 1KX14 A/D 18DIP

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Sheet目录3862

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1997 Microchip Technology Inc.

DS30272A-page 53

PIC16C71X

8.4

Power-on Reset (POR), Power-up

Timer (PWRT) and Oscillator Start-up

Timer (OST), and Brown-out Reset

(BOR)

8.4.1

POWER-ON RESET (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.5V - 2.1V). To

take advantage of the POR, just tie the MCLR pin

directly (or through a resistor) to VDD. This will eliminate

external RC components usually needed to create a

Power-on Reset. A maximum rise time for VDD is spec-

ied. See Electrical Specications for details.

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature, ...) must be met to ensure

operation. If these conditions are not met, the device

must be held in reset until the operating conditions are

met. Brown-out Reset may be used to meet the startup

conditions.

For additional information, refer to Application Note

AN607, "

Power-up Trouble Shooting."

8.4.2

POWER-UP TIMER (PWRT)

The Power-up Timer provides a xed 72 ms nominal

time-out on power-up only, from the POR. The Power-

up Timer operates on an internal RC oscillator. The

chip is kept in reset as long as the PWRT is active. The

PWRT’s time delay allows VDD to rise to an acceptable

level. A conguration bit is provided to enable/disable

the PWRT.

Applicable Devices

710 71 711 715

Applicable Devices

710 71 711 715

The power-up time delay will vary from chip to chip due

to VDD, temperature, and process variation. See DC

parameters for details.

8.4.3

OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal oscil-

lator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

8.4.4

BROWN-OUT RESET (BOR)

A conguration bit, BODEN, can disable (if clear/pro-

grammed) or enable (if set) the Brown-out Reset cir-

cuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for

greater than parameter #35, the brown-out situation will

reset the chip. A reset may not occur if VDD falls below

4.0V for less than parameter #35. The chip will remain

in Brown-out Reset until VDD rises above BVDD. The

Power-up Timer will now be invoked and will keep the

chip in RESET an additional 72 ms. If VDD drops below

BVDD while the Power-up Timer is running, the chip will

go back into a Brown-out Reset and the Power-up

Timer will be initialized. Once VDD rises above BVDD,

the Power-up Timer will execute a 72 ms time delay.

The Power-up Timer should always be enabled when

Brown-out Reset is enabled. Figure 8-10 shows typical

brown-out situations.

Applicable Devices

710 71 711 715

Applicable Devices

710 71 711 715

FIGURE 8-10: BROWN-OUT SITUATIONS

72 ms

BVDD

VDD

Internal

Reset

BVDD

VDD

Internal

Reset

72 ms

<72 ms

72 ms

BVDD

VDD

Internal

Reset

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